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d1306hkim 20060919-s00005 no.a0429-1/35 lc75835w overview the lc75835w is a 1/3, 1/4 duty general-purpose lcd display driver that can be used for displaying segments for mobile devices and other such products under the control of a microcontroller. in addition to being able to directly drive up to 136 lcd segments, the lc75835w can also control up to 16 general-purpose output ports. it incorporates an oscillation circuit that reduces the external re sistors and capacitors used for oscillation. features ? either 1/4 or 1/3 duty can be sel ected with the serial control data. 1/4 duty drive: up to 136 segments can be driven 1/3 duty drive: up to 105 segments can be driven ? either 1/3 or 1/2 bias can be selected with the serial control data. ? on, off, or blinking for each segment can be set with the serial control data. ? serial data control of display switching in 40-bit units. (as a general rule, the display can be switched in 12 segment-units.) ? serial data control of current on/off to the lcd drive bias voltage generation divider resistors. ? serial data control of the power-saving mode based backup function and the all segments forced off function. ? serial data control of switching between the segment output port and general-purpose output port functions. ? buzzer control signals (1 channel) can be output from the general-purpose output port. ? serial data control of the frame frequency of the common and segment output waveforms. ? serial data control of the segment blinking frequency. ? serial data control of switching between the internal oscillator operating mode and external clock operating mode. ? serial data input supports ccb* format communication with the system controller. ? independent v lcd for the lcd driver block (v lcd can be set to any voltage in the range 2.7 to 5.5 volts without regard to the logic block power supply v dd ). ? the inh pin allows the display to be forced to the off state. ? incorporation of an oscillator circuit ordering number : ENA0429 cmos ic 1/3, 1/4-duty general-purpose lcd display driver ? ccb is a trademark of sanyo electric co., ltd. ? ccb is sanyo's original bus format and all the bus addresses are controlled by sanyo. any and all sanyo semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo semiconductor representative nearest you before using any sanyo semiconductor products described or contained herein in such applications. sanyo semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated val ues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor products described or contained herein.
lc75835w no.a0429-2/35 specifications absolute maximum ratings at ta = 25 c, v ss = 0v parameter symbol conditions ratings unit v dd max v dd -0.3 to +4.5 maximum supply voltage v lcd max v lcd -0.3 to +6.5 v v in 1 ce, cl, di, inh , osci -0.3 to +4.5 input voltage v in 2 v lcd 1, v lcd 2 -0.3 to v lcd +0.3 v output voltage v out s1 to s35, com1 to com4, p1 to p16 -0.3 to v lcd +0.3 v i out 1 s1 to s35 300 a i out 2 com1 to com4 3 output current i out 3 p1 to p16 *1 5 ma allowable power dissipation pd max ta = 75 c 100 mw operating temperature topr -30 to +75 c storage temperature tstg -55 to +125 c note: * 1 the sum of output current through p1 to p16 must be 40ma or less. allowable operating ranges at ta = -30 to +75 c, v ss = 0v ratings parameter symbol conditions min typ max unit v dd v dd 2.7 3.6 supply voltage v lcd v lcd 2.7 5.5 v v lcd 1 v lcd 1 2/3v lcd v lcd input voltage v lcd 2 v lcd 2 1/3v lcd v lcd v v ih 1 ce, cl, di, inh 0.7v dd 3.6 input high-level voltage v ih 2 osci 0.7v dd 3.6 v v il 1 ce, cl, di, inh 0 0.2v dd input low-level voltage v il 2 osci 0 0.2v dd v external clock operating frequency f ck osci external clock operating mode [figure 4] 15 32.8 65 khz external clock duty cycle d ck osci external clock operating mode [figure 4] 30 50 70 % data setup time tds cl, di [figure 2][figure 3] 160 ns data hold time tdh cl, di [figure 2][figure 3] 160 ns ce wait time tcp ce, cl [figure 2][figure 3] 160 ns ce setup time tcs ce, cl [figure 2][figure 3] 160 ns ce hold time tch ce, cl [figure 2][figure 3] 160 ns high-level clock pulse width t h cl [figure 2][figure 3] 160 ns low-level clock pulse width t l cl [figure 2][figure 3] 160 ns rise time tr ce, cl, di [figure 2][figure 3] 160 ns fall time tf ce, cl, di [figure 2][figure 3] 160 ns inh switching time tc inh , ce [figure 5][figure 6] 10 s
lc75835w no.a0429-3/35 electrical characteristics for the allowable operating ranges ratings parameter symbol pin conditions min typ max unit hysteresis v h ce, cl, di, inh 0.1v dd v i ih 1 ce, cl, di, inh v i = 3.6v 1.0 input high-level current i ih 2 osci v i = 3.6v 1.0 a i il 1 ce, cl, di, inh v i = 0v -1.0 input low-level current i il 2 osci v i = 0v -1.0 a v oh 1 s1 to s35 i o = -20 a v lcd -0.9 v oh 2 com1 to com4 i o = -100 a v lcd -0.9 output high-level voltage v oh 3 p1 to p16 i o = -1ma v lcd -0.9 v v ol 1 s1 to s35 i o = 20 a 0.9 v ol 2 com1 to com4 i o = 100 a 0.9 output low-level voltage v ol 3 p1 to p16 i o = 1ma 0.9 v v mid 1 com1 to com4 1/2 bias i o = 100 a 1/2v lcd -0.9 1/2v lcd +0.9 v mid 2 s1 to s35 1/3 bias i o = 20 a 2/3v lcd -0.9 2/3v lcd +0.9 v mid 3 s1 to s35 1/3 bias i o = 20 a 1/3v lcd -0.9 1/3v lcd +0.9 v mid 4 com1 to com4 1/3 bias i o = 100 a 2/3v lcd -0.9 2/3v lcd +0.9 output middle-level voltage *2 v mid 5 com1 to com4 1/3 bias i o = 100 a 1/3v lcd -0.9 1/3v lcd +0.9 v v lcd 1 v lcd 1 1/3 bias i i = 0 a current supply to bias voltage generation divider resistors outputs open 2/3v lcd -0.03v lcd 2/3v lcd 2/3v lcd +0.03v lcd v lcd 2 v lcd 2 1/3 bias i i = 0 a current supply to bias voltage generation divider resistors outputs open 1/3v lcd -0.03v lcd 1/3v lcd 1/3v lcd +0.03v lcd lcd drive bias voltage v lcd 12 v lcd 1, v lcd 2 1/2 bias i i = 0 a current supply to bias voltage generation divider resistors outputs open 1/2v lcd -0.03v lcd 1/2v lcd 1/2v lcd +0.03v lcd v oscillator frequency fosc internal oscillator circuit internal oscillator operating mode 236 295 354 khz i dd 1 v dd power-saving mode 1 i dd 2 v dd v dd = 3.3v normal mode external clock operating mode *3 5 10 i dd 3 v dd v dd = 3.3v normal mode external clock operating mode *3 serial data transfer *4 90 180 i dd 4 v dd v dd = 3.3v normal mode internal oscillator operating mode 50 100 i dd 5 vdd v dd = 3.3v normal mode internal oscillator operating mode serial data transfer *4 135 270 i lcd 1 v lcd power-saving mode 1 i lcd 2 v lcd v lcd = 5.0v output open normal mode, 1/2 bias 85 170 i lcd 3 v lcd v lcd = 5.0v output open normal mode, 1/3 bias 55 110 current drain i lcd 4 v lcd v lcd = 5.0v output open normal mode, current to bias voltage generation divider resistors shut off 10 20 a note: * 2 excluding the bias voltage generation divider resistors (r lcd = 30k ? typ.) built in the v lcd 1 and v lcd 2. (see figure 1.) note: * 3 external clock operating mode (f ck = 32.8khz, v ih 2 = v dd , v il 2 = 0v, rise/fall time = 20ns) note: * 4 serial data transfer (data transfer frequency 2mhz, v ih 1 = v dd , v il 1 = 0v, rise/fall time = 20ns)
lc75835w no.a0429-4/35 figure 1 1. when cl is stopped at the low level figure 2 2. when cl is stopped at the high level figure 3 3. osci pin clock timing in external clock operating mode figure 4 v ss to the common and segment drivers v lcd 1 except these resistors. v lcd v lcd 2 r l c d r l c d r l c d r lcd = 30k ? 100[%] v il 2 50% v ih 2 tds v il 1 v il 1 v il 1 v ih 1 v ih 1 50% v ih 1 tch tcs tcp tdh tr tf t h t l ce cl di l t
lc75835w no.a0429-5/35 package dimensions unit : mm (typ) 3163b pin assignment com4/s35 com3 com1 s23 s24 com2 s22 s21 s20 v dd v l c d v l c d 1 v l c d 2 lc75835w v ss osci inh ce cl 36 25 37 24 13 12 1 48 di s33 s34 s30 s31 s32 s26 s27 s25 p11/s11 p12/s12 s28 s29 s19 s18 s17 s16/p16 s15/p15 s14/p14 s13/p13 p7/s7 p8/s8 p9/s9 p10/s10 p5/s5 p6/s6 p3/s3 p4/s4 p1/s1 p2/s2 top view sanyo : sqfp48(7x7) 7.0 7.0 9.0 9.0 0.15 0.5 (1.5) 0.1 1.7max 0.18 0.5 (0.75) 112 13 24 25 36 37 48
lc75835w no.a0429-6/35 block diagram s1/p1 s2/p2 s16/p16 s17 ce cl di com4/s35 com3 com2 com1 v ss v lcd 2 v lcd 1 v lcd inh osci shift register segment driver & latch ccb interface clock generator common driver s34 control register v dd
lc75835w no.a0429-7/35 pin functions symbol pin no. function active i/o handling when unused s1/p1 to s16/p16 s17 to s34 1 to 16 17 to 34 segment outputs for displaying the display dat a transferred by serial data input. the s1/p1 to s16/p16 pins can be used as general-purpose output ports when so set up by the control data. - o open com1 to com3 com4/s35 38 to 36 35 common driver output pins. the frame fr equency is fo [hz]. com4/s35 can be used as segment output in 1/3 duty mode. - o open osci 44 external clock input pin. a 15 to 65khz clock must be supplied to this pin in external clock operating mode. this pin must be connected to ground in internal oscillator operating mode. - i gnd ce cl di 46 47 48 serial data transfer inputs. must be connected to the controller. ce: chip enable cl: synchronization clock di: transfer data h - i i i gnd inh 45 display off control input ? inh = low (v ss ) ...display forced off s1/p1 to s16/p16 = low (v ss ) (these pins are forcibly set to the general-purpose output port and held at the vss level.) s17 to s34 = low (v ss ) com1 to com3 = low (v ss ) com4/s35 = low (v ss ) shuts off current to the lcd drive bias voltage generation divider resistors. stop the internal oscillation circuit. ? inh = high (v dd )...display on however, serial data transfer is possible when the display is forced off. l i gnd v lcd 1 41 used to apply the lcd drive 2/3 bias voltage externally. connect this pin to v lcd 2 when using a 1/2-bias drive scheme. - i open v lcd 2 42 used to apply the lcd drive 1/3 bias voltage externally. connect this pin to v lcd 1 when using a 1/2-bias drive scheme. - i open v dd 39 power supply pin for the logic circuit block. a power voltage of 2.7v to 3.6v must be applied to this pin. - - - v lcd 40 power supply pin for the lcd driver block. a power voltage of 2.7v to 5.5 v must be applied to this pin. - - - v ss 43 power supply pin. must be connected to ground. - - -
lc75835w no.a0429-8/35 serial data transfer formats (1) 1/4 duty 1. when cl is stopped at the low level ? when the display data is transferred display data 24 bit ccb address 8 bit di cl ce 1 b 0 fixed data 4 bit dd 4 bit 1 0 0 0 0 1 0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 0 0 0 0 0 0 0 1 b1 b2 b 3 a 0 a1 a2 a 3 display data 24 bit ccb address 8 bit di cl ce 1 b 0 1 0 0 0 0 1 0 d25 d26 d27 d28 d29 d30 d31 d32 d33 d34 d35 d36 d37 d38 d39 d40 d41 d42 d43 d44 d45 d46 d47 d48 0 0 0 0 0 0 1 0 b1 b2 b 3 a 0 a1 a2 a 3 fixed data 4 bit dd 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d49 d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 d64 d65 d66 d67 d68 d69 d70 d71 d72 0 0 0 0 0 0 1 1 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b 0 1 0 0 0 0 1 0 d73 d74 d75 d76 d77 d78 d79 d80 d81 d82 d83 d84 d85 d86 d87 d88 d89 d90 d91 d92 d93 d94 d95 d96 0 0 0 0 0 1 0 0 b1 b2 b 3 a 0 a1 a2 a 3 fixed data 4 bit dd 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b 0 1 0 0 0 0 1 0 d97 d98 d99 d100 d101 d102 d103 d104 d105 d106 d107 d108 d109 d110 d111 d112 d113 d114 d115 d116 d117 d118 d119 d120 0 0 0 0 0 1 0 1 b1 b2 b 3 a 0 a1 a2 a 3 fixed data 4 bit dd 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d121 d122 d123 d124 d125 d126 d127 d128 d129 d130 d131 d132 d133 d134 d135 d136 d137 d138 d139 d140 d141 d142 d143 d144 0 0 0 0 0 1 1 0 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b 0 1 0 0 0 0 1 0 d145 d146 d147 d148 d149 d150 d151 d152 d153 d154 d155 d156 d157 d158 d159 d160 d161 d162 d163 d164 d165 d166 d167 d168 0 0 0 0 0 1 1 1 b1 b2 b 3 a 0 a1 a2 a 3 fixed data 4 bit dd 4 bit fixed data 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b 0 1 0 0 0 0 1 0 d169 d170 d171 d172 d173 d174 d175 d176 d177 d178 d179 d180 d181 d182 d183 d184 d185 d186 d187 d188 d189 d190 d191 d192 0 0 0 0 1 0 0 0 b1 b2 b 3 a 0 a1 a2 a 3 dd 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d193 d194 d195 d196 d197 d198 d199 d200 d201 d202 d203 d204 d205 d206 d207 d208 d209 d210 d211 d212 d213 d214 d215 d216 0 0 0 0 1 0 0 1 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit
lc75835w no.a0429-9/35 ? when the control data is transferred note: dd is the direction data. ? ccb address ....... "46h" ? d1 to d272 ......... display data ? pc1 to pc16......... ge neral-purpose output po rt state setting data ? ps1 to ps16 ......... segment output port/gener al-purpose output port switching control data ? pz0 to pz4 ......... buzzer contro l signal output selection data ? pzf ................ ...... buzzer control signal fr equency setting control data ? dr ...................... 1/3-bias drive or 1/2-bias drive switching control data ? dt ...................... 1/4-duty drive or 1/3-duty drive switching control data ? oc ................ ...... internal oscillator opera ting mode/external clock operatin g mode switching control data ? fc0, fc1 ......... common/segment output wa veform frame frequency setting control data ? bf0, bf1 ......... segment blinki ng frequency setting control data ? sc ...................... segment on/off control data ? bc ...................... lcd drive bias voltage genera tion divider resistor current on/off control data ? bu ...................... normal mode/power-saving mode control data display data 24 bit ccb address 8 bit di cl ce 1 b 0 1 0 0 0 0 1 0 d217 d218 d219 d220 d221 d222 d223 d224 d225 d226 d227 d228 d229 d230 d231 d232 d233 d234 d235 d236 d237 d238 d239 d240 0 0 0 0 1 0 1 0 b1 b2 b 3 a 0 a1 a2 a 3 fixed data 12 bit display data 16 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d241 d242 d243 d244 d245 d246 d247 d248 d249 d250 d251 d252 d253 d254 d255 d256 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 b1 b2 b3 a0 a1 a2 a3 display data 16 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d257 d258 d259 d260 d261 d262 d263 d264 d265 d266 d267 d268 d269 d270 d271 d272 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit dd 4 bit fixed data 12 bit dd 4 bit control data 48 bit ccb address 8 bit di cl ce 1 b 0 1 0 0 0 0 1 0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pc8 pc9 pc10 pc11 pc12 pc13 pc14 pc15 pc16 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 ps12 ps13 ps14 ps15 ps16 b1 b2 b 3 a 0 a1 a2 a 3 fixed data 4 bit pz0 pz1 pz2 pz3 pz4 pzf dr dt oc fc0 fc1 bf0 bf1 sc bc bu 0 0 0 0 0 0 0 0 dd 4 bit
lc75835w no.a0429-10/35 2. when cl is stopped at the high level ? when the display data is transferred display data 24 bit ccb address 8 bit di cl ce 1 b 0 fixed data 4 bit dd 4 bit 1 0 0 0 0 1 0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 0 0 0 0 0 0 0 1 b1 b2 b 3 a 0 a1 a2 a 3 display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d25 d26 d27 d28 d29 d30 d31 d32 d33 d34 d35 d36 d37 d38 d39 d40 d41 d42 d43 d44 d45 d46 d47 d48 0 0 0 0 0 0 1 0 b1 b2 b3 a0 a1 a2 a3 display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d49 d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 d64 d65 d66 d67 d68 d69 d70 d71 d72 0 0 0 0 0 0 1 1 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit fixed data 4 bit dd 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b 0 1 0 0 0 0 1 0 d73 d74 d75 d76 d77 d78 d79 d80 d81 d82 d83 d84 d85 d86 d87 d88 d89 d90 d91 d92 d93 d94 d95 d96 0 0 0 0 0 1 0 0 b1 b2 b 3 a 0 a1 a2 a 3 display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d97 d98 d99 d100 d101 d102 d103 d104 d105 d106 d107 d108 d109 d110 d111 d112 d113 d114 d115 d116 d117 d118 d119 d120 0 0 0 0 0 1 0 1 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit fixed data 4 bit dd 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d121 d122 d123 d124 d125 d126 d127 d128 d129 d130 d131 d132 d133 d134 d135 d136 d137 d138 d139 d140 d141 d142 d143 d144 0 0 0 0 0 1 1 0 b1 b2 b3 a0 a1 a2 a3 display data 24 bit ccb address 8 bit di cl ce 1 b 0 1 0 0 0 0 1 0 d145 d146 d147 d148 d149 d150 d151 d152 d153 d154 d155 d156 d157 d158 d159 d160 d161 d162 d163 d164 d165 d166 d167 d168 0 0 0 0 0 1 1 1 b1 b2 b 3 a 0 a1 a2 a 3 fixed data 4 bit dd 4 bit fixed data 4 bit dd 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d169 d170 d171 d172 d173 d174 d175 d176 d177 d178 d179 d180 d181 d182 d183 d184 d185 d186 d187 d188 d189 d190 d191 d192 0 0 0 0 1 0 0 0 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d193 d194 d195 d196 d197 d198 d199 d200 d201 d202 d203 d204 d205 d206 d207 d208 d209 d210 d211 d212 d213 d214 d215 d216 0 0 0 0 1 0 0 1 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit
lc75835w no.a0429-11/35 ? when the control data is transferred note: dd is the direction data. ? ccb address ....... "46h" ? d1 to d272 ......... display data ? pc1 to pc16......... ge neral-purpose output po rt state setting data ? ps1 to ps16 ......... segment output port/gener al-purpose output port switching control data ? pz0 to pz4 ......... buzzer contro l signal output selection data ? pzf ................ ...... buzzer control signal fr equency setting control data ? dr ...................... 1/3-bias drive or 1/2-bias drive switching control data ? dt ...................... 1/4-duty drive or 1/3-duty drive switching control data ? oc ................ ...... internal oscillator opera ting mode/external clock operatin g mode switching control data ? fc0, fc1 ......... common/segment output wa veform frame frequency setting control data ? bf0, bf1 ......... segment blinki ng frequency setting control data ? sc ...................... segment on/off control data ? bc ...................... lcd drive bias voltage genera tion divider resistor current on/off control data ? bu ...................... normal mode/power-saving mode control data display data 24 bit ccb address 8 bit di cl ce 1 b 0 1 0 0 0 0 1 0 d217 d218 d219 d220 d221 d222 d223 d224 d225 d226 d227 d228 d229 d230 d231 d232 d233 d234 d235 d236 d237 d238 d239 d240 0 0 0 0 1 0 1 0 b1 b2 b 3 a 0 a1 a2 a 3 fixed data 12 bit display data 16 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d241 d242 d243 d244 d245 d246 d247 d248 d249 d250 d251 d252 d253 d254 d255 d256 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 b1 b2 b3 a0 a1 a2 a3 display data 16 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d257 d258 d259 d260 d261 d262 d263 d264 d265 d266 d267 d268 d269 d270 d271 d272 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit dd 4 bit fixed data 12 bit dd 4 bit control data 48 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 pc1 0 pc2 pc3 pc4 pc5 pc6 pc7 pc8 pc9 pc10 pc11 pc12 pc13 pc14 pc15 pc16 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 ps12 ps13 ps14 ps15 ps16 b1 b2 b3 a0 a1 a2 a3 pz0 pz1 pz2 pz3 pz4 pzf dr dt oc fc0 fc1 bf0 bf1 sc bc bu 0 0 0 0 0 0 0 0 fixed data 4 bit dd 4 bit
lc75835w no.a0429-12/35 (2) 1/3 duty 1. when cl is stopped at the low level ? when the display data is transferred display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 0 0 0 0 0 0 0 1 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d25 d26 d27 d28 d29 d30 d31 d32 d33 d34 d35 d36 d37 d38 d39 d40 d41 d42 d43 d44 d45 d46 d47 d48 0 0 0 0 0 0 1 0 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d49 d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 d64 d65 d66 d67 d68 d69 d70 d71 d72 0 0 0 0 0 0 1 1 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d73 d74 d75 d76 d77 d78 d79 d80 d81 d82 d83 d84 d85 d86 d87 d88 d89 d90 d91 d92 d93 d94 d95 d96 0 0 0 0 0 1 0 0 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d97 d98 d99 d100 d101 d102 d103 d104 d105 d106 d107 d108 d109 d110 d111 d112 d113 d114 d115 d116 d117 d118 d119 d120 0 0 0 0 0 1 0 1 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d121 d122 d123 d124 d125 d126 d127 d128 d129 d130 d131 d132 d133 d134 d135 d136 d137 d138 d139 d140 d141 d142 d143 d144 0 0 0 0 0 1 1 0 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d145 d146 d147 d148 d149 d150 d151 d152 d153 d154 d155 d156 d157 d158 d159 d160 d161 d162 d163 d164 d165 d166 d167 d168 0 0 0 0 0 1 1 1 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d169 d170 d171 d172 d173 d174 d175 d176 d177 d178 d179 d180 d181 d182 d183 d184 d185 d186 d187 d188 d189 d190 d191 d192 0 0 0 0 1 0 0 0 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit fixed data 10 bit display data 18 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d193 d194 d195 d196 d197 d198 d199 d200 d201 d202 d203 d204 d205 d206 d207 d208 d209 d210 0 0 0 0 0 0 0 0 0 0 1 0 0 1 b1 b2 b3 a0 a1 a2 a3 dd 4 bit
lc75835w no.a0429-13/35 ? when the control data is transferred note: dd is the direction data. ? ccb address ....... "46h" ? d1 to d210 ......... display data ? pc1 to pc16......... ge neral-purpose output po rt state setting data ? ps1 to ps16 ......... segment output port/gener al-purpose output port switching control data ? pz0 to pz4 ......... buzzer contro l signal output selection data ? pzf ................ ...... buzzer control signal fr equency setting control data ? dr ...................... 1/3-bias drive or 1/2-bias drive switching control data ? dt ...................... 1/4-duty drive or 1/3-duty drive switching control data ? oc ................ ...... internal oscillator opera ting mode/external clock operatin g mode switching control data ? fc0, fc1 ......... common/segment output wa veform frame frequency setting control data ? bf0, bf1 ......... segment blinki ng frequency setting control data ? sc ...................... segment on/off control data ? bc ...................... lcd drive bias voltage genera tion divider resistor current on/off control data ? bu ...................... normal mode/power-saving mode control data control data 48 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pc8 pc9 pc10 pc11 pc12 pc13 pc14 pc15 pc16 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 ps12 ps13 ps14 ps15 ps16 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit pz0 pz1 pz2 pz3 pz4 pzf dr dt oc fc0 fc1 bf0 bf1 sc bc bu 0 0 0 0 0 0 0 0 dd 4 bit
lc75835w no.a0429-14/35 2. when cl is stopped at the high level ? when the display data is transferred display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 0 0 0 0 0 0 0 1 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d25 d26 d27 d28 d29 d30 d31 d32 d33 d34 d35 d36 d37 d38 d39 d40 d41 d42 d43 d44 d45 d46 d47 d48 0 0 0 0 0 0 1 0 b1 b2 b3 a0 a1 a2 a3 display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d49 d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 d64 d65 d66 d67 d68 d69 d70 d71 d72 0 0 0 0 0 0 1 1 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit fixed data 4 bit dd 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d73 d74 d75 d76 d77 d78 d79 d80 d81 d82 d83 d84 d85 d86 d87 d88 d89 d90 d91 d92 d93 d94 d95 d96 0 0 0 0 0 1 0 0 b1 b2 b3 a0 a1 a2 a3 display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d97 d98 d99 d100 d101 d102 d103 d104 d105 d106 d107 d108 d109 d110 d111 d112 d113 d114 d115 d116 d117 d118 d119 d120 0 0 0 0 0 1 0 1 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit fixed data 4 bit dd 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d121 d122 d123 d124 d125 d126 d127 d128 d129 d130 d131 d132 d133 d134 d135 d136 d137 d138 d139 d140 d141 d142 d143 d144 0 0 0 0 0 1 1 0 b1 b2 b3 a0 a1 a2 a3 display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d145 d146 d147 d148 d149 d150 d151 d152 d153 d154 d155 d156 d157 d158 d159 d160 d161 d162 d163 d164 d165 d166 d167 d168 0 0 0 0 0 1 1 1 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit fixed data 4 bit dd 4 bit display data 24 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d169 d170 d171 d172 d173 d174 d175 d176 d177 d178 d179 d180 d181 d182 d183 d184 d185 d186 d187 d188 d189 d190 d191 d192 0 0 0 0 1 0 0 0 b1 b2 b3 a0 a1 a2 a3 fixed data 4 bit dd 4 bit fixed data 10 bit display data 18 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 0 d193 d194 d195 d196 d197 d198 d199 d200 d201 d202 d203 d204 d205 d206 d207 d208 d209 d210 0 0 0 0 0 0 0 0 0 0 1 0 0 1 b1 b2 b3 a0 a1 a2 a3 dd 4 bit
lc75835w no.a0429-15/35 ? when the control data is transferred note: dd is the direction data. ? ccb address ....... "46h" ? d1 to d210 ......... display data ? pc1 to pc16......... ge neral-purpose output po rt state setting data ? ps1 to ps16 ......... segment output port/gener al-purpose output port switching control data ? pz0 to pz4 ......... buzzer contro l signal output selection data ? pzf ................ ...... buzzer control signal fr equency setting control data ? dr ...................... 1/3-bias drive or 1/2-bias drive switching control data ? dt ...................... 1/4-duty drive or 1/3-duty drive switching control data ? oc ................ ...... internal oscillator opera ting mode/external clock operatin g mode switching control data ? fc0, fc1 ......... common/segment output wa veform frame frequency setting control data ? bf0, bf1 ......... segment blinki ng frequency setting control data ? sc ...................... segment on/off control data ? bc ...................... lcd drive bias voltage genera tion divider resistor current on/off control data ? bu ...................... normal mode/power-saving mode control data control data 48 bit ccb address 8 bit di cl ce 1 b0 1 0 0 0 0 1 pc1 0 pc2 pc3 pc4 pc5 pc6 pc7 pc8 pc9 pc10 pc11 pc12 pc13 pc14 pc15 pc16 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 ps12 ps13 ps14 ps15 ps16 b1 b2 b3 a0 a1 a2 a3 pz0 pz1 pz2 pz3 pz4 pzf dr dt oc fc0 fc1 bf0 bf1 sc bc bu 0 0 0 0 0 0 0 0 fixed data 4 bit dd 4 bit
lc75835w no.a0429-16/35 serial data transfer example (1) 1/4 duty ? when 129 or more segments are used all 544 bits of serial data (including ccb address) must be sent. ? when fewer than 12 9 segments are used depending on the number of segments used, 104 bits, 144 bits, 184 bits, 224 bits, 264 bits, 304 bits, 344 bits, 384 bits, 424 bits, 464 bits or 504 bits (including the ccb address) must be sent as serial data. however, the serial data (control data) shown in the figure below must be sent without fail. note: after the above serial data is sent, the contents of the display data can be changed by transferring only the serial data (ccb addresses, display data, fixed data, and directio n data) including the display data to be changed in 40-bit units. 56 bit 8 bit d2 d1 d7 0 1 1 0 0 0 1 0 b0 b1 b2 b3 a 0 a1 a2 a3 d8 d9 d10 d11 d3 d4 d5 d6 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 0 0 0 0 0 0 0 1 d26 d25 d31 0 1 1 0 0 0 1 0 b0 b1 b2 b3 a 0 a1 a2 a3 d32 d33 d34 d35 d27 d28 d29 d30 d36 d37 d38 d39 d40 d41 d42 d43 d44 d45 d46 d47 d48 0 0 0 0 0 0 1 0 d50 d49 d55 0 1 1 0 0 0 1 0 d56 d57 d58 d59 d51 d52 d53 d54 d60 d61 d62 d63 d64 d65 d66 d67 d68 d69 d70 d71 d72 0 0 0 0 0 0 1 1 d74 d73 d79 0 1 1 0 0 0 1 0 d80 d81 d82 d83 d75 d76 d77 d78 d84 d85 d86 d87 d88 d89 d90 d91 d92 d93 d94 d95 d96 0 0 0 0 0 1 0 0 d98 d97 0 1 1 0 0 0 1 0 d99 d100 d101 0 0 0 0 0 1 0 1 d102 d103 d104 d105 d106 d107 d108 d109 d110 d111 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 0 1 1 0 0 0 1 0 d124 d125 0 0 0 0 0 1 1 0 d126 d127 d128 d129 d130 d131 d132 d133 d134 d135 d136 d137 d138 d139 d140 d141 d142 d143 d144 d122 d123 b0 b1 b2 b3 a 0 a1 a2 a3 b0 b1 b2 b3 a 0 a1 a2 a3 b0 b1 b2 b3 a 0 a1 a2 a3 b0 b1 b2 b3 a 0 a1 a2 a3 d145 0 1 1 0 0 0 1 0 d148 d149 0 0 0 0 0 1 1 1 d150 d151 d152 d153 d154 d155 d156 d157 d158 d159 d160 d161 d162 d163 d164 d165 d166 d167 d168 d146 d147 b0 b1 b2 b3 a 0 a1 a2 a3 d169 0 1 1 0 0 0 1 0 d172 d173 0 0 0 0 1 0 0 0 d174 d175 d176 d177 d178 d179 d180 d181 d182 d183 d184 d185 d186 d187 d188 d189 d190 d191 d192 d170 d171 b0 b1 b2 b3 a 0 a1 a2 a3 d193 0 1 1 0 0 0 1 0 d196 d197 0 0 0 0 1 0 0 1 d198 d199 d200 d201 d202 d203 d204 d205 d206 d207 d208 d209 d210 d211 d212 d213 d214 d215 d216 d194 d195 b0 b1 b2 b3 a 0 a1 a2 a3 d217 0 1 1 0 0 0 1 0 d220 d221 0 0 0 0 1 0 1 0 d222 d223 d224 d225 d226 d227 d228 d229 d230 d231 d232 d233 d234 d235 d236 d237 d238 d239 d240 d218 d219 b0 b1 b2 b3 a 0 a1 a2 a3 d241 0 1 1 0 0 0 1 0 d244 d245 0 0 0 0 1 0 1 1 d246 d247 d248 d249 d250 d251 d252 d253 d254 d255 d256 00000000 d242 d243 b0 b1 b2 b3 a 0 a1 a2 a3 d257 0 1 1 0 0 0 1 0 d260 d261 0 0 0 0 1 1 0 0 d262 d263 d264 d265 d266 d267 d268 d269 d270 d271 d272 00000000 d258 d259 b0 b1 b2 b3 a 0 a1 a2 a3 pc1 0 1 1 0 0 0 1 0 b0 b1 b2 b3 a 0 a1 a2 a3 pc2 pc3 pc4 pc5 pc6 pc7 pc8 pc9 pc10 pc11 pc12 pc13 pc14 pc15 pc16 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 0 0 0 0 pz0 pz1 pz2 pz3 pz4 pzf dr dt oc fc0 fc1 bf0 bf1 sc bc bu 0 0 0 0 ps12 ps13 ps14 ps15 ps16 32 bit 8 bit 56 bit 8 bit pc1 0 1 1 0 0 0 1 0 b0 b1 b2 b3 a 0 a1 a2 a3 pc2 pc3 pc4 pc5 pc6 pc7 pc8 pc9 pc10 pc11 pc12 pc13 pc14 pc15 pc16 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 0 0 0 0 pz0 pz1 pz2 pz3 pz4 pzf dr dt oc fc0 fc1 bf0 bf1 sc bc bu 0 0 0 0 ps12 ps13 ps14 ps15 ps16
lc75835w no.a0429-17/35 (2) 1/3 duty ? when 97 or more segments are used all 424 bits of serial data (including ccb addresses) must be sent. ? when fewer than 97 segments are used depending on the number of segments used, 104 bits, 144 bits, 184 bits, 224 bits, 264 bits, 304 bits, 344 bits or 384 bits (including the ccb address) must be sent as se rial data. however, the seri al data (control data) shown in the figure below must be sent without fail. note: after the above serial data is sent, the contents of the display data can be changed by transferring only the serial data (ccb addresses, display data, fixed data, and directio n data) including the display data to be changed in 40-bit units. 56 bit 8 bit d2 d1 d7 0 1 1 0 0 0 1 0 b0 b1 b2 b3 a 0 a1 a2 a3 d8 d9 d10 d11 d3 d4 d5 d6 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 0 0 0 0 0 0 0 1 d26 d25 d31 0 1 1 0 0 0 1 0 b0 b1 b2 b3 a 0 a1 a2 a3 d32 d33 d34 d35 d27 d28 d29 d30 d36 d37 d38 d39 d40 d41 d42 d43 d44 d45 d46 d47 d48 0 0 0 0 0 0 1 0 d50 d49 d55 0 1 1 0 0 0 1 0 d56 d57 d58 d59 d51 d52 d53 d54 d60 d61 d62 d63 d64 d65 d66 d67 d68 d69 d70 d71d72 0 0 0 0 0 0 1 1 d74 d73 d79 0 1 1 0 0 0 1 0 d80 d81 d82 d83 d75 d76 d77 d78 d84 d85 d86 d87 d88 d89 d90 d91 d92 d93 d94 d95 d96 0 0 0 0 0 1 0 0 d98 d97 0 1 1 0 0 0 1 0 d99 d100 d101 0 0 0 0 0 1 0 1 d102 d103 d104 d105 d106 d107 d108 d109 d110 d111 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 0 1 1 0 0 0 1 0 d124 d125 0 0 0 0 0 1 1 0 d126 d127 d128 d129 d130 d131 d132 d133 d134 d135 d136 d137 d138 d139 d140 d141 d142 d143 d144 d122 d123 b0 b1 b2 b3 a 0 a1 a2 a3 b0 b1 b2 b3 a 0 a1 a2 a3 b0 b1 b2 b3 a 0 a1 a2 a3 b0 b1 b2 b3 a 0 a1 a2 a3 d145 0 1 1 0 0 0 1 0 d148 d149 0 0 0 0 0 1 1 1 d150 d151 d152 d153 d154 d155 d156 d157 d158 d159 d160 d161 d162 d163 d164 d165 d166 d167 d168 d146 d147 b0 b1 b2 b3 a 0 a1 a2 a3 d169 0 1 1 0 0 0 1 0 d172 d173 0 0 0 0 1 0 0 0 d174 d175 d176 d177 d178 d179 d180 d181 d182 d183 d184 d185 d186 d187 d188 d189 d190 d191 d192 d170 d171 b0 b1 b2 b3 a 0 a1 a2 a3 d193 0 1 1 0 0 0 1 0 d196 d197 0 0 0 0 1 0 0 1 d198 d199 d200 d201 d202 d203 d204 d205 d206 d207 d208 d209 d210 000000 d194 d195 b0 b1 b2 b3 a 0 a1 a2 a3 pc1 0 1 1 0 0 0 1 0 b0 b1 b2 b3 a 0 a1 a2 a3 pc2 pc3 pc4 pc5 pc6 pc7 pc8 pc9 pc10 pc11 pc12 pc13 pc14 pc15 pc16 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 0 0 0 0 pz0 pz1 pz2 pz3 pz4 pzf dr dt oc fc0 fc1 bf0 bf1 sc bc bu 0 0 0 0 ps12 ps13 ps14 ps15 ps16 32 bit 8 bit 56 bit 8 bit pc1 0 1 1 0 0 0 1 0 b0 b1 b2 b3 a 0 a1 a2 a3 pc2 pc3 pc4 pc5 pc6 pc7 pc8 pc9 pc10 pc11 pc12 pc13 pc14 pc15 pc16 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 0 0 0 0 pz0 pz1 pz2 pz3 pz4 pzf dr dt oc fc0 fc1 bf0 bf1 sc bc bu 0 0 0 0 ps12 ps13 ps14 ps15 ps16
lc75835w no.a0429-18/35 control data functions 1. pc1 to pc16: general-purpose output port state setting data this control data is used to set the ?h? and ?l? status of general-purpose output ports p1 to p16. output pin p1 p2 p3 p4 p5 p6 p7 p8 control data pc1 pc2 pc 3 pc4 pc5 pc6 pc7 pc8 output pin p9 p10 p11 p12 p13 p14 p15 p16 control data pc9 pc10 pc 11 pc12 pc13 pc14 pc15 pc16 notes: pcn = ?1?: ?h? (v lcd ) is output from output pin pn (n = 1 to 16). pcn = ?0?: ?l? (v ss ) is output from output pin pn (n = 1 to 16). if, for instance, output pins s4/p4 and s5/p5 have been selected as the general-purpose output ports at pc4 = ?1? and pc5 = ?0?, ?h? (v lcd ) is output from output pin p4 and ?l? (v ss ) is output from output pin p5. 2. ps1 to ps16: segment output port/general-purpose output port switching control data this control data is used to switch between segment output ports and general-purpose output ports for the s1/p1 to s16/p16 output pins. output pin s1/p1 s2/p2 s3/p3 s4/p4 s5/p5 s6/p6 s7/p7 s8/p8 control data ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 output pin s9/p9 s10/p10 s11/p11 s12/ p12 s13/p13 s14/p14 s15/p15 s16/p16 control data ps9 ps10 ps11 ps12 ps13 ps14 ps15 ps16 notes: psn = ?1?: general-purpose output port pn is selected for output pin sn/pn (n = 1 to 16). psn = ?0?: segment output port sn is selected for output pin sn/pn (n = 1 to 16). if, for instance, ps1 to ps3 = ?0?, ps4, ps5 = ?1? and ps6 to ps16 = ?0?, general-purpose output ports are selected for output pins s4/p4 and s5/p5 and segment output ports are selected for output pins s1/p1 to s3/p3 and s6/p6 to s16/p16. 3. pz0 to pz4: buzzer contro l signal output selection data this control data is used to select the general-purpose output ports from which the buzzer control signals (square waves with a 50% duty ratio) are output. control data control data pz0 pz1 pz2 pz3 pz4 general-purpose output ports from which buzzer control signals are output pz0 pz1 pz2 pz3 pz4 general-purpose output ports from which buzzer control signals are output 1 0 0 0 0 p1 1 0 0 1 0 p9 0 1 0 0 0 p2 0 1 0 1 0 p10 1 1 0 0 0 p3 1 1 0 1 0 p11 0 0 1 0 0 p4 0 0 1 1 0 p12 1 0 1 0 0 p5 1 0 1 1 0 p13 0 1 1 0 0 p6 0 1 1 1 0 p14 1 1 1 0 0 p7 1 1 1 1 0 p15 0 0 0 1 0 p8 0 0 0 0 1 p16 note: data other than the data listed above must be se t if the buzzer control signal s are not to be output. for example, set (pz0, pz1, pz2, pz3, pz4) = (0, 0, 0, 0, 0). 4. pzf: buzzer control signal frequency setting control data this control data bit sets the frequency of the buzzer control signals (square waves with a 50% duty ratio). pzf buzzer control signal frequency fz [hz] 0 fosc/144, f ck /16 1 fosc/72, f ck /8 note: fosc: internal oscillation frequency (295 [khz] typ.), f ck : external clock operating frequency (32.8 [khz] typ.)
lc75835w no.a0429-19/35 5. dr: 1/3 bias drive or 1/2 bias drive switching control data this control data bit selects either 1/3 bias drive or 1/2 bias drive. dr bias drive scheme 0 1/3 bias drive 1 1/2 bias drive 6. dt: 1/4 duty drive or 1/3 duty drive switching control data this control data bit selects either 1/4 duty drive or 1/3 duty drive. dt duty drive scheme output pin (com4/s35) status 0 1/4 duty drive com4 (common output) 1 1/3 duty drive s35 (segment output) 7. oc: internal oscillator operating mode/external clock operating mode switching control data this control data bit selects either internal oscillator operating mode or external clock operating mode. oc basic clock operation m ode input pin (osci) status 0 internal oscillator operating mode must be connected to gnd. 1 external clock operating mode the clock signal (15 to 65 [khz]) must be input from an external source. 8. fc0, fc1: common/segment output waveform frame frequency setting control data these control data bits set the frame frequency for common and segment output waveforms. control data frame frequency fo [hz] fc0 fc1 1/4 duty drive 1/3 duty drive 0 0 fosc/5760, f ck /640 fosc/5670, f ck /630 1 0 fosc/4608, f ck /512 fosc/4536, f ck /504 0 1 fosc/3456, f ck /384 fosc/3402, f ck /378 1 1 fosc/2304, f ck /256 fosc/2268, f ck /252 note: fosc: internal oscillation frequency (295 [khz] typ.), f ck : external clock operating frequency (32.8 [khz] typ.) 9. bf0, bf1: segment blinking frequency setting control data theses control data bits control the segment blinking frequency. control data bf0 bf1 segment blinking frequency fb [hz] 0 0 fosc/184320, f ck /20480 1 0 fosc/147456, f ck /16384 0 1 fosc/110592, f ck /12288 1 1 fosc/73728, f ck /8192 note: fosc: internal oscillation frequency (295 [khz] typ.), f ck : external clock operating frequency (32.8 [khz] typ.) 10. sc: segment on/off control data this control data bit controls the on/off state of the segments. sc display state 0 on 1 off note that when the segments are turned off by setting sc to ?1?, the segments are turned off by outputting segment off waveforms from the segment output pins. 11. bc: lcd drive bias voltage generation divider resistor current on/off control data this control data is used to turn on/off the current to the lcd drive bias voltage generation divider resistors. bc lcd drive bias voltage generation divider resister state 0 turns on current to the divider resistors. 1 turns off current to the divider resistors.
lc75835w no.a0429-20/35 12. bu: normal mode/power-saving mode control data this control data bit selects either normal mode or power-saving mode. bu mode 0 normal mode 1 power-saving mode in internal oscillator operating mode (oc = ?0?), the oscillation of the internal oscillation circuit is stopped; in external clock operating mode (oc = ?1?), the acceptance of the ex ternal clock is stopped. t he common or segment output pins go to the v ss level. in addition, the current to the lcd drive bias voltage generation divider resistors is turned off. however, the output pins s1/p1 to s16/p16 can be used as general-purpose output ports (the output of a buzzer control signal is impossible.) under the control of control data bits ps1 to ps16. display data and output pin correspondence 1. 1/4 duty output pin com1 com2 com3 com4 s1/p1 d1 d2 d3 d4 d5 d6 d7 d8 s2/p2 d9 d10 d11 d 12 d13 d14 d15 d16 s3/p3 d17 d18 d19 d 20 d21 d22 d23 d24 s4/p4 d25 d26 d27 d 28 d29 d30 d31 d32 s5/p5 d33 d34 d35 d 36 d37 d38 d39 d40 s6/p6 d41 d42 d43 d 44 d45 d46 d47 d48 s7/p7 d49 d50 d51 d 52 d53 d54 d55 d56 s8/p8 d57 d58 d59 d 60 d61 d62 d63 d64 s9/p9 d65 d66 d67 d 68 d69 d70 d71 d72 s10/p10 d73 d74 d75 d76 d77 d78 d79 d80 s11/p11 d81 d82 d83 d84 d85 d86 d87 d88 s12/p12 d89 d90 d91 d92 d93 d94 d95 d96 s13/p13 d97 d98 d99 d100 d101 d102 d103 d104 s14/p14 d105 d106 d107 d108 d109 d110 d111 d112 s15/p15 d113 d114 d115 d116 d117 d118 d119 d120 s16/p16 d121 d122 d123 d124 d125 d126 d127 d128 s17 d129 d130 d131 d 132 d133 d134 d135 d136 s18 d137 d138 d139 d 140 d141 d142 d143 d144 s19 d145 d146 d147 d 148 d149 d150 d151 d152 s20 d153 d154 d155 d 156 d157 d158 d159 d160 s21 d161 d162 d163 d 164 d165 d166 d167 d168 s22 d169 d170 d171 d 172 d173 d174 d175 d176 s23 d177 d178 d179 d 180 d181 d182 d183 d184 s24 d185 d186 d187 d 188 d189 d190 d191 d192 s25 d193 d194 d195 d 196 d197 d198 d199 d200 s26 d201 d202 d203 d 204 d205 d206 d207 d208 s27 d209 d210 d211 d 212 d213 d214 d215 d216 s28 d217 d218 d219 d 220 d221 d222 d223 d224 s29 d225 d226 d227 d 228 d229 d230 d231 d232 s30 d233 d234 d235 d 236 d237 d238 d239 d240 s31 d241 d242 d243 d 244 d245 d246 d247 d248 s32 d249 d250 d251 d 252 d253 d254 d255 d256 s33 d257 d258 d259 d 260 d261 d262 d263 d264 s34 d265 d266 d267 d 268 d269 d270 d271 d272 note: the applies to the case where the s1/p1 to s16/p16 output pins are set to be segment output ports.
lc75835w no.a0429-21/35 for example, the table below lists the segment output states for the s11 output pin. display data d81 d82 d83 d84 d85 d86 d87 d88 segment output pin (s11) state 0 0 0 0 0 0 0 0 the lcd segments corresponding to com1, com2, com3, and com4 are off. 1 0 1 0 1 0 1 0 the lcd segments corresponding to com1, com2, com3, and com4 are on. x 1 x 1 x 1 x 1 the lcd segments for com1, com2, com3, and com4 are blinking. 1 0 0 0 0 0 0 0 the lcd segment corresponding to com1 is on. the lcd segments corresponding to com2, com3, and com4 are off. x 1 0 0 0 0 0 0 the lcd segment for com1 is blinking. the lcd segments corresponding to com2, com3, and com4 are off. 0 0 1 0 0 0 0 0 the lcd segment corresponding to com2 is on. the lcd segments corresponding to com1, com3, and com4 are off. 0 0 x 1 0 0 0 0 the lcd segment for com2 is blinking. the lcd segments corresponding to com1, com3, and com4 are off. 0 0 0 0 1 0 0 0 the lcd segment corresponding to com3 is on. the lcd segments corresponding to com1, com2, and com4 are off. 0 0 0 0 x 1 0 0 the lcd segment for com3 is blinking. the lcd segments corresponding to com1, com2, and com4 are off. 0 0 0 0 0 0 1 0 the lcd segment corresponding to com4 is on. the lcd segments corresponding to com1, com2, and com3 are off. 0 0 0 0 0 0 x 1 the lcd segment for com4 is blinking. the lcd segments corresponding to com1, com2, and com3 are off. 1 0 1 0 0 0 0 0 the lcd segments corresponding to com1 and com2 are on. the lcd segments corresponding to com3 and com4 are off. 0 0 1 0 1 0 0 0 the lcd segments corresponding to com2 and com3 are on. the lcd segments corresponding to com1 and com4 are off. 0 0 0 0 1 0 1 0 the lcd segments corresponding to com3 and com4 are on. the lcd segments corresponding to com1 and com2 are off. 1 0 0 0 0 0 1 0 the lcd segments corresponding to com1 and com4 are on. the lcd segments corresponding to com2 and com3 are off. 1 0 x 1 0 0 0 0 the lcd segment corresponding to com1 is on. the lcd segment for com2 is blinking. the lcd segments corresponding to com3 and com4 are off. 0 0 1 0 x 1 0 0 the lcd segment corresponding to com2 is on. the lcd segment for com3 is blinking. the lcd segments corresponding to com1 and com4 are off. 0 0 0 0 1 0 x 1 the lcd segment corresponding to com3 is on. the lcd segment for com4 is blinking. the lcd segments corresponding to com1 and com2 are off. x 1 0 0 0 0 1 0 the lcd segment corresponding to com4 is on. the lcd segment for com1 is blinking. the lcd segments corresponding to com2 and com3 are off. note: x: don?t care
lc75835w no.a0429-22/35 2. 1/3 duty output pin com1 com2 com3 s1/p1 d1 d2 d3 d4 d5 d6 s2/p2 d7 d8 d9 d10 d11 d12 s3/p3 d13 d14 d15 d16 d17 d18 s4/p4 d19 d20 d21 d22 d23 d24 s5/p5 d25 d26 d27 d28 d29 d30 s6/p6 d31 d32 d33 d34 d35 d36 s7/p7 d37 d38 d39 d40 d41 d42 s8/p8 d43 d44 d45 d46 d47 d48 s9/p9 d49 d50 d51 d52 d53 d54 s10/p10 d55 d56 d57 d58 d59 d60 s11/p11 d61 d62 d63 d64 d65 d66 s12/p12 d67 d68 d69 d70 d71 d72 s13/p13 d73 d74 d75 d76 d77 d78 s14/p14 d79 d80 d81 d82 d83 d84 s15/p15 d85 d86 d87 d88 d89 d90 s16/p16 d91 d92 d93 d94 d95 d96 s17 d97 d98 d99 d100 d101 d102 s18 d103 d104 d105 d106 d107 d108 s19 d109 d110 d111 d112 d113 d114 s20 d115 d116 d117 d118 d119 d120 s21 d121 d122 d123 d124 d125 d126 s22 d127 d128 d129 d130 d131 d132 s23 d133 d134 d135 d136 d137 d138 s24 d139 d140 d141 d142 d143 d144 s25 d145 d146 d147 d148 d149 d150 s26 d151 d152 d153 d154 d155 d156 s27 d157 d158 d159 d160 d161 d162 s28 d163 d164 d165 d166 d167 d168 s29 d169 d170 d171 d172 d173 d174 s30 d175 d176 d177 d178 d179 d180 s31 d181 d182 d183 d184 d185 d186 s32 d187 d188 d189 d190 d191 d192 s33 d193 d194 d195 d196 d197 d198 s34 d199 d200 d201 d202 d203 d204 s35/com4 d205 d206 d207 d208 d209 d210 note: the applies to the case where the s1/p1 to s16/p16 and s35/com4 output pins are set to be segment output ports.
lc75835w no.a0429-23/35 for example, the table below lists the segment output states for the s11 output pin. display data d61 d62 d63 d64 d65 d66 segment output pin (s11) state 0 0 0 0 0 0 the lcd segments corresponding to com1, com2, and com3 are off. 1 0 1 0 1 0 the lcd segments corresponding to com1, com2, and com3 are on. x 1 x 1 x 1 the lcd segments for com1, com2, and com3 are blinking. 1 0 0 0 0 0 the lcd segment corresponding to com1 is on. the lcd segments corresponding to com2 and com3 are off. x 1 0 0 0 0 the lcd segment for com1 is blinking. the lcd segments corresponding to com2 and com3 are off. 0 0 1 0 0 0 the lcd segment corresponding to com2 is on. the lcd segments corresponding to com1 and com3 are off. 0 0 x 1 0 0 the lcd segment for com2 is blinking. the lcd segments corresponding to com1 and com3 are off. 0 0 0 0 1 0 the lcd segment corresponding to com3 is on. the lcd segments corresponding to com1 and com2 are off. 0 0 0 0 x 1 the lcd segment for com3 is blinking. the lcd segments corresponding to com1 and com2 are off. 1 0 1 0 0 0 the lcd segments corresponding to com1 and com2 are on. the lcd segment corresponding to com3 is off. 0 0 1 0 1 0 the lcd segments corresponding to com2 and com3 are on. the lcd segment corresponding to com1 is off. 1 0 0 0 1 0 the lcd segments corresponding to com1 and com3 are on. the lcd segment corresponding to com2 is off. 1 0 x 1 0 0 the lcd segment corresponding to com1 is on. the lcd segment for com2 is blinking. the lcd segment corresponding to com3 is off. 0 0 1 0 x 1 the lcd segment corresponding to com2 is on. the lcd segment for com3 is blinking. the lcd segment corresponding to com1 is off. x 1 0 0 1 0 the lcd segment corresponding to com3 is on. the lcd segment for com1 is blinking. the lcd segment corresponding to com2 is off. note: x: don?t care
lc75835w no.a0429-24/35 output waveforms (1/4-dut y 1/3-bias drive scheme) control data fc0 fc1 frame frequency fo [hz] 0 0 fosc/5760, f ck /640 1 0 fosc/4608, f ck /512 0 1 fosc/3456, f ck /384 1 1 fosc/2304, f ck /256 note: fosc: internal oscillation frequency (295 [khz] typ.), f ck : external clock operating frequency (32.8 [khz] typ.) v lcd 1 v lcd 2 fo[hz] v lcd com3 com2 com1 com4 lcd driver output when all lcd segments corresponding to com1, com2, com3, and com4 are on. lcd driver output when lcd segments corresponding to com2 and com4 are on. lcd driver output when only lcd segments corresponding to com4 are on. lcd driver output when lcd segments corresponding to com1, com2, and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when only lcd segments corresponding to com1 are on. lcd driver output when all lcd segments corresponding to com1, com2, com3, and com4 are off. 0v v lcd 1 v lcd 2 v lcd 0v v lcd 1 v lcd 2 v lcd 0v v lcd 1 v lcd 2 v lcd 0v v lcd 1 v lcd 2 v lcd 0v v lcd 1 v lcd 2 v lcd 0v v lcd 1 v lcd 2 v lcd 0v v lcd 1 v lcd 2 v lcd 0v v lcd 1 v lcd 2 v lcd 0v v lcd 1 v lcd 2 v lcd 0v v lcd 1 v lcd 2 v lcd 0v v lcd 1 v lcd 2 v lcd 0v v lcd 1 v lcd 2 v lcd 0v v lcd 1 v lcd 2 v lcd 0v v lcd 1 v lcd 2 v lcd 0v
lc75835w no.a0429-25/35 output waveforms (1/4-dut y 1/2-bias drive scheme) control data fc0 fc1 frame frequency fo [hz] 0 0 fosc/5760, f ck /640 1 0 fosc/4608, f ck /512 0 1 fosc/3456, f ck /384 1 1 fosc/2304, f ck /256 note: fosc: internal oscillation frequency (295 [khz] typ.), f ck : external clock operating frequency (32.8 [khz] typ.) v lcd 1,v lcd 2 v lcd com3 com2 com1 com4 0v fo[hz] v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v lcd driver output when all lcd segments corresponding to com1, com2, com3, and com4 are on. lcd driver output when lcd segments corresponding to com2 and com4 are on. lcd driver output when only lcd segments corresponding to com4 are on. lcd driver output when lcd segments corresponding to com1, com2, and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when only lcd segments corresponding to com1 are on. lcd driver output when all lcd segments corresponding to com1, com2, com3, and com4 are off.
lc75835w no.a0429-26/35 output waveforms (1/3-dut y 1/3-bias drive scheme) control data fc0 fc1 frame frequency fo [hz] 0 0 fosc/5670, f ck /630 1 0 fosc/4536, f ck /504 0 1 fosc/3402, f ck /378 1 1 fosc/2268, f ck /252 note: fosc: internal oscillation frequency (295 [khz] typ.), f ck : external clock operating frequency (32.8 [khz] typ.) com3 com2 com1 fo[hz] v lcd 2 v lcd 1 v lcd 0v v lcd 2 v lcd 1 v lcd 0v v lcd 2 v lcd 1 v lcd 0v v lcd 2 v lcd 1 v lcd 0v v lcd 2 v lcd 1 v lcd 0v v lcd 2 v lcd 1 v lcd 0v v lcd 2 v lcd 1 v lcd 0v v lcd 2 v lcd 1 v lcd 0v v lcd 2 v lcd 1 v lcd 0v v lcd 2 v lcd 1 v lcd 0v v lcd 2 v lcd 1 v lcd 0v lcd driver output when all lcd segments corresponding to com1, com2, and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when only lcd segments corresponding to com1 are on. lcd driver output when all lcd segments corresponding to com1, com2, and com3 are off.
lc75835w no.a0429-27/35 output waveforms (1/3-dut y 1/2-bias drive scheme) control data fc0 fc1 frame frequency fo [hz] 0 0 fosc/5670, f ck /630 1 0 fosc/4536, f ck /504 0 1 fosc/3402, f ck /378 1 1 fosc/2268, f ck /252 note: fosc: internal oscillation frequency (295 [khz] typ.), f ck : external clock operating frequency (32.8 [khz] typ.) com3 com2 com1 lcd driver output when all lcd segments corresponding to com1, com2, and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when all lcd segments corresponding to com1, com2, and com3 are off. lcd driver output when only lcd segments corresponding to com1 are on. lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. v lcd 1,v lcd 2 v lcd 0v fo[hz] v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v v lcd 1,v lcd 2 v lcd 0v
lc75835w no.a0429-28/35 the inh pin and display control since the ic internal data (1/4 duty: the display data d1 to d272 and the control data, 1/3 duty: the display data d1 to d210 and the control data) is undefined when power is first applied, applications should set the inh pin low at the same time as power is applied to turn off the display (this sets the s1/p1 to s16/p16, s17 to s34, com1 to com3, and com4/s35 to the v ss level.) and during this period send serial data from the controller. the controller should then set the inh pin high after the data transfer has completed. this procedure prevents meaningless displays at power on. (see figures 5 and 6.) notes on the power on/off sequences applications should observe the following sequences when turning the lc75835w power on and off. (see figures 5 and 6) ? at power on: logic block power supply (v dd ) on lcd driver block power supply (v lcd ) on ? at power off: lcd driver block power supply (v lcd ) off logic block power supply (v dd ) off however, if the logic and lcd driver block use a shared power supply, then the power supplies can be turned on and off at the same time. 1. 1/4 duty figure 5 0 t2>0 t3 0 (t2>t3) tc ??? 10 s min t1 display data and control data transfer v dd t2 pc1 to pc16,ps1 to ps16, internal data pz0 to pz4,pzf,dr,dt,oc, fc0,fc1,bf0,bf1,sc,bc,bu internal data (d1 to d24) internal data (d25 to d48) v lcd ce inh undefined defined undefined v il 1 tc v il 1 t3 undefined defined undefined undefined defined undefined internal data (d241 to d256) undefined defined undefined internal data (d257 to d272) undefined defined undefined
lc75835w no.a0429-29/35 2. 1/3 duty figure 6 n ote: t1 0 t2>0 t3 0 (t2>t3) tc ??? 10 s min t1 display data and control data transfer v dd t2 pc1 to pc16,ps1 to ps16, internal data pz0 to pz4,pzf,dr,dt,oc, fc0 , fc1 , bf0 , bf1 , sc , bc , bu internal data (d1 to d24) internal data (d25 to d48) v lcd ce inh undefined defined undefined v il 1 tc v il 1 t3 undefined defined undefined undefined defined undefined internal data (d169 to d192) undefined defined undefined internal data (d193 to d210) undefined defined undefined
lc75835w no.a0429-30/35 notes on controller transf er of display data since the lc75835w accepts th e display data (d1 to d272) di vided into 12 separate transf er operations when using 1/4 duty drive scheme and data (d1 to d210) divided into 9 separate transfer operations when using 1/3 duty drive scheme, we recommend that the applications tran sfer all of the display data within a period of less than 30ms to prevent observable degradation of display quality. generation of buzzer control signal a square wave with a 50% duty ratio is output from the general-purpose output port selected for the output of the buzzer control signal between the start and end of the buzzer control signal output. if, for example, general-purpose output port p1 has been selected as the output of the buzzer control signal (pc1 = ?0?, ps1 = ?1?), the waveform shown below will be output. control data pzf buzzer control signal frequency fz(=1/tz)[hz] 0 fosc/144, f ck /16 1 fosc/72, f ck /8 note: fosc: internal oscillation frequency (295 [khz] typ.), f ck : external clock operating frequency (32.8 [khz] typ.) oscillation stabilization time of the internal oscillation circuit it must be noted that the oscillation of the internal oscillation circuit is unstable for a maximum of 100 s (oscillation stabilization time) after oscillation has started. p1 tz/2 tz tz/2 tz/2 tz/2 tz tz/2 tz/2 tz tz/2 tz tz/2 beginning of buzzer control signal generation (send control data pz0, pz1, pz2, pz3, pz4 ("1,0,0,0,0")) end of buzzer control signal generation (send control data pz0, pz1, pz2, pz3, pz4 ("0,0,0,0,0")) internal oscillation circuit oscillation stabilization time (100 [ s] max.) 1. if the inh pin status is switched from ?l? to ?h? when control data oc = ?0? and bu = ?0? 2. if the control data bu is set from ?1? to ?0? when inh = ?h? and control data oc = ?0? oscillation operation (under normal conditions) oscillation stopped
lc75835w no.a0429-31/35 sample application circuit 1 1/4 duty, 1/3 bias (when the lcd drive bias voltage is not supplied from an external source) * 5: the osci pin must be connected to gnd when the intern al oscillator operating mode (oc = ?0?) has been selected; the clock must be input from an external source when the external clock operating mode (oc = ?1?) has been selected. * 6: control data bc must be set to ?0?. sample application circuit 2 1/4 duty, 1/3 bias (when the lcd drive bias voltage is supplied from an external source) * 5: the osci pin must be connected to gnd when the intern al oscillator operating mode (oc = ?0?) has been selected; the clock must be input from an external source when the external clock operating mode (oc = ?1?) has been selected. * 6: control data bc must be set to ?1?. c from the controlle r c 0.047 f +5v +3.3v c di cl ce inh v lcd 2 v lcd 1 v lcd v ss s34 s33 s17 p16/s16 p2/s2 p1/s1 com3 com2 general-purpose output ports (p16) (p2) (p1) com1 v dd used for functions such as backlight control s35/com4 *5 osci external clock input lcd panel (up to 136 segments) c from the controlle r 100k ? r 1k ? c 0.047 f +5v +3.3v r r r c di cl ce inh v lcd 2 v lcd 1 v lcd v ss s34 s33 s17 p16/s16 p2/s2 p1/s1 com3 com2 general-purpose output ports (p16) (p2) (p1) com1 v dd s35/com4 *5 osci external clock input used for functions such as backlight control lcd panel (up to 136 segments)
lc75835w no.a0429-32/35 sample application circuit 3 1/4 duty, 1/2 bias (when the lcd drive bias voltage is not supplied from an external source) * 5: the osci pin must be connected to gnd when the intern al oscillator operating mode (oc = ?0?) has been selected; the clock must be input from an external source when the external clock operating mode (oc = ?1?) has been selected. * 6: control data bc must be set to ?0?. sample application circuit 4 1/4 duty, 1/2 bias (when the lcd drive bias voltage is supplied from an external source) * 5: the osci pin must be connected to gnd when the intern al oscillator operating mode (oc = ?0?) has been selected; the clock must be input from an external source when the external clock operating mode (oc = ?1?) has been selected. * 6: control data bc must be set to ?1?. from the controlle r c +5v +3.3v di cl ce inh v lcd 2 v lcd 1 v lcd v ss s34 s33 s17 p16/s16 p2/s2 p1/s1 com3 com2 general-purpose output ports (p16) (p2) (p1) com1 v dd s35/com4 *5 osci external clock input used for functions such as backlight control c 0.047 f lcd panel (up to 136 segments) c from the controlle r +5v +3.3v r r di cl ce inh v lcd 2 v lcd 1 v lcd v ss s34 s33 s17 p16/s16 p2/s2 p1/s1 com3 com2 general-purpose output ports (p16) (p2) (p1) com1 v dd s35/com4 *5 osci external clock input used for functions such as backlight control 100k ? r 1k ? c 0.047 f lcd panel (up to 136 segments)
lc75835w no.a0429-33/35 sample application circuit 5 1/3 duty, 1/3 bias (when the lcd drive bias voltage is not supplied from an external source) * 5: the osci pin must be connected to gnd when the intern al oscillator operating mode (oc = ?0?) has been selected; the clock must be input from an external source when the external clock operating mode (oc = ?1?) has been selected. * 6: control data bc must be set to ?0?. sample application circuit 6 1/3 duty, 1/3 bias (when the lcd drive bias voltage is supplied from an external source) * 5: the osci pin must be connected to gnd when the intern al oscillator operating mode (oc = ?0?) has been selected; the clock must be input from an external source when the external clock operating mode (oc = ?1?) has been selected. * 6: control data bc must be set to ?1?. c from the controlle r +5v +3.3v c di cl ce inh v lcd 2 v lcd 1 v lcd v ss com4/s35 s34 s33 s17 p16/s16 p2/s2 p1/s1 com3 com2 general-purpose output ports (p16) (p2) (p1) com1 v dd *5 osci external clock input c 0.047 f used for functions such as backlight control lcd panel (up to 105 segments) c from the controlle r +5v +3.3v r r r c di cl ce inh v lcd 2 v lcd 1 v lcd v ss com4/s35 s34 s33 s17 p16/s16 p2/s2 p1/s1 com3 com2 general-purpose output ports (p16) (p2) (p1) com1 v dd *5 osci external clock input 100k ? r 1k ? c 0.047 f used for functions such as backlight control lcd panel (up to 105 segments)
lc75835w no.a0429-34/35 sample application circuit 7 1/3 duty, 1/2 bias (when the lcd drive bias voltage is not supplied from an external source) * 5: the osci pin must be connected to gnd when the intern al oscillator operating mode (oc = ?0?) has been selected; the clock must be input from an external source when the external clock operating mode (oc = ?1?) has been selected. * 6: control data bc must be set to ?0?. sample application circuit 8 1/3 duty, 1/2 bias (when the lcd drive bias voltage is supplied from an external source) * 5: the osci pin must be connected to gnd when the intern al oscillator operating mode (oc = ?0?) has been selected; the clock must be input from an external source when the external clock operating mode (oc = ?1?) has been selected. * 6: control data bc must be set to ?1?. from the controlle r c di cl ce inh v lcd 2 v lcd 1 v lcd v ss com4/s35 s34 s33 s17 p16/s16 p2/s2 p1/s1 com3 com2 general-purpose output ports (p16) (p2) (p1) com1 +5v +3.3v v dd *5 osci external clock input c 0.047 f used for functions such as backlight control lcd panel (up to 105 segments) c from the controlle r +5v +3.3v r r di cl ce inh v lcd 2 v lcd 1 v lcd v ss com4/s35 s34 s33 s17 p16/s16 p2/s2 p1/s1 com3 com2 general-purpose output ports (p16) (p2) (p1) com1 v dd *5 osci external clock input 100k ? r 1k ? c 0.047 f used for functions such as backlight control lcd panel (up to 105 segments)
lc75835w no.a0429-35/35 ps this catalog provides information as of december, 2006. specifications and information herein are subject to change without notice. specifications of any and all sanyo semiconductor pr oducts described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. to verify s ymptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. sanyo semiconductor co., ltd. strives to supply high- quality high-reliability products. however, any and all semiconductor products fail with some probabi lity. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property . when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor produc ts (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording , or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo semiconductor co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo semiconductor product that you intend to use. information (including circuit diagrams and circui t parameters) herein is for example only; it is not guaranteed for volume production. sanyo semicondu ctor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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